(1) Field of the Invention
The invention relates to digital integrated circuits, and more particularly, to a circuit that allows a digital signal to be level shifted from a low voltage supply to a high voltage supply.
(2) Description of the Prior Art
Ultra deep submicron CMOS technologies are used to create digital integrated circuits with very high transistor densities and very high switching speeds. These submicron CMOS transistors have very thin gate oxide and very low threshold voltages. To facilitate use of ultra deep submicron CMOS processes, the supply voltage for the high density logic core must be lowered to improve device reliability. Supply voltages of between about 2.5 Volts and 3.3 Volts, which have been typical for prior art CMOS logic devices, have to be reduced to a low voltage regime of, for example, between about 0.9 Volts and 2.5 Volts.
While the supply voltage of the core logic section is being reduced, the supply voltage for the input/output section of the integrated circuit must be kept at a higher level to assure adequate signal-to-noise ratio and compatibility with other devices. Where digital signals in the low voltage core must be transmitted off the integrated circuit, signal level shifting is therefore necessary. A level shifting circuit is used to increase the upper voltage swing of the low voltage signal, from a low voltage to a high voltage.
Referring now to FIG. 1, a prior art level shifting circuit is shown. This level shifting circuit uses four types of transistors. Low voltage NMOS transistors 10 and low voltage PMOS transistors 14 are used in the low supply voltage VCCL 34 section. High voltage NMOS transistors 18 and high voltage PMOS transistors 22 are used in the high supply voltage VCCH section. The low voltage transistors 10 and 14 have a thinner gate oxide than the high voltage transistors 18 and 22. In addition, the low voltage transistors 10 and 14 have a low threshold voltage of between about 0.2 Volts and 0.35 Volts for NMOS 10 and between about xe2x88x920.2 Volts and xe2x88x920.35 Volts for PMOS 14. High voltage devices have a threshold voltage of between about 0.4 Volts and 0.7 Volts for NMOS 18 and between about xe2x88x920.4 Volts and xe2x88x920.7 Volts for PMOS 22.
The prior art level shifting circuit uses an inverter made up of transistors MN1 46 and MP1 50 and a differential pair made up of transistors MN2 54, MN3 58, MP2 62, and MP3 66. Generally, the low voltage supply VCCL 34 is biased at between about 0.9 Volts and 2.5 Volts. The high voltage supply VCCH 42 is biased at between about 3 Volts and 5 Volts. The purpose of the level shifting circuit is to convert the input signal IN 26 from a swing of between 0 Volts and VCCL 34 to a swing of between 0 Volts and VCCH 42 at the output node OUT 30.
The prior art level shifting circuit exhibits dc voltage and transistor switching characteristics according to Table 1 below:
Note that the prior art level shifting circuit exhibits no dc static current consumption. Since the input signal IN 26 only connects to the gates of transistors MN1 46, MP1 50, and MN2 54, there is no dc input leakage path. Only one of the inverter pair MN1 46 and MP1 50 is ON in either state. Therefore, there exists no static current path from VCCL 34 to VSS 38. Finally, since only the pair MN2 54 and MP3 66 or the pair MN3 58 and MP2 62 are ON at any given time, there exists no static current path between VCCH and VSS.
Note also that the high supply voltage VCCH is only applied to the thick oxide devices MN2 54, MN3 58, MP2 62 and MP3 66. Therefore, reliability concerns for the thin oxide devices are eliminated.
To illustrate the ac performance of the prior art level shifting circuit, consider the case of the input signal IN 26 switching from VSS to VCCL. First, transistor MN2 54 turns ON. At this point, transistor MP2 62 remains ON. Therefore, while MN2 54 is driving node OUTB 28 to VSS, MP2 62 is concurrently driving node OUTB 28 to VCCL. After transistor MP1 50 turns OFF, the inverter output INB 27 transitions to VSS. Transistor MN3 58 is therefore turned OFF. Finally, once the voltage at node OUTB 28 is discharged, transistor MP3 66 is turned ON. MP3 66 drives the output node OUT 30 to VCCH and turns OFF MP2 62.
An analysis of the ac operation of the prior art level shifting circuit reveals a serious switching delay when the design is used in an ultra-deep submicron process. In such processes, the VCCL 34 voltage is very small to facilitate the usage of very small devices with very thin gate oxides, shallow junctions, and shrinking threshold voltages. However, the key input transistors of the circuit, MN2 54 and MN3 58, still have large voltage thresholds. Therefore, the Idsat of these thick gate NMOS devices, at the relatively small gate drive of VCCL, is also small. If, as in the example case, MN2 54 must drive node OUTB 28 against MP2 62, then the reduced Idsat of MN2 54 will cause the OUTB signal transition to take a long time.
In addition, since OUTB 28 initially remains at or near VCCH 42, transistor MP3 66 is OFF. At the same time, transistor MN3 58 is in the off-state once INB 27 discharges to VSS. In this condition, the output node OUT 30 is floating. The voltage level of OUT 30 will depend on the load and the reverse saturation current of the MP3 66 drain-to-N Well and the MN3 58 drain-to-P Well junction diodes during the transition time prior to MN2 54 discharging OUTB 28 to VSS.
Finally, the Idsat of MN2 54 and of MN3 58 may be made larger than the Idsat of MP2 62 and of MP3 66 by making MN2 and MN3 sufficiently large to overcome the relatively small gate drive. However, this adds substantially to the area required for the level shifting circuit. In addition, the parasitic capacitance from the gate of MP3 66 and the drain junction of MP2 62 must be discharged by MN2 54 during a transition.
Several prior art inventions describe circuits for level shifting and handling higher voltage supplies in low voltage CMOS applications. U.S. Pat. No. 6,043,699 to Shimizu describes level shifting circuits with higher speed or with extended operating ranges. U.S. Pat. No. 6,043,698 to Hill teaches a level shifting circuit using a latch and resistors in the interface section. U.S. Pat. No. 5,892,371 to Maley discloses a level shifting circuit configured to protect MOS transistors from gate oxide failure by limiting the voltage across any one transistor. U.S. Pat. No. 5,729,155 to Kobatake describes a level shifting circuit where an NMOS transistor and a PMOS transistor are connected in series between the top rail PMOS transistor and the bottom rail NMOS transistor. The additional transistors are biased to fixed voltage references to insure that each device is ON. The presence of the transistor pair reduces the voltage stress on each device in the stack. U.S. Pat. No. 5,539,334 to Clapp, III et al discloses a circuit, comprising low voltage components, that can be used with a high voltage supply. The level shifting circuit embodiment may accommodate multiple power supplies. U.S. Pat. No. 5,821,800 to Le et al teaches a level shifting circuit capable of high voltage operation using low voltage CMOS devices. One or more complementary NMOS and PMOS pairs are used between the top rail PMOS and the bottom rail NMOS transistors. The complementary devices are not self-biased. U.S. Pat. No. 5,153,451 to Yamamura et al describes a level shifting circuit that has a fail-safe mode. The output state is guaranteed high or guaranteed low if the input signal voltage falls below a predetermined level. U.S. Pat. No. 5,698,993 to Chow discloses a level shifting circuit where an NMOS transistor is added to each side of the differential pair to improve switching speed and symmetry. The gates of the added NMOS devices are biased to a constant low voltage supply. U.S. Pat. No. 5,705,946 to Yin teaches a two-stage level shifter using a voltage divider input. U.S. Pat. No. 5,917,339 to Kim describes a mixed voltage input buffer. U.S. Pat. No. 5,963,061 to Briner discloses a level shifting circuit using complementary NMOS and PMOS transistor pairs stacked between the rail devices as guard devices to limit high voltage exposure. The complementary pairs may be biased to the same constant voltage source or to independent constant voltage sources. U.S. Pat. No. 5,963,054 to Cochran et al teaches a circuit for switching voltages greater than the gate oxide breakdown of the MOS transistors will allow. A transistor pair is disposed between the PMOS and NMOS switching transistors. U.S. Pat. No. 5,450,357 to Coffman describes a level shifting circuit for selecting different voltage levels for programming memory cells.
A principal object of the present invention is to provide a level shifting circuit, that is, a circuit that allows a digital signal to be level shifted from a low voltage supply to a high voltage supply.
A further object of the present invention is to provide a level shifting circuit that can interface ultra-deep submicron devices and high voltage devices.
A yet further object of the present invention is to provide a level shifting circuit with higher switching speed.
Another yet further object of the present invention is to provide a level shifting circuit with a reduced area.
Another yet further object of the present invention is to provide a level shifting circuit with high reliability.
Another yet further object of the present invention is to provide a level shifting circuit with no static current draw.
In accordance with the objects of this invention, a new level shifting circuit, using dynamic current compensation, is described. An input swings between a low supply and ground. An output swings between a high supply and ground. An inverter has an input and an output. The input is connected to the input of the level shifting circuit, and the output forms an inverted level shifting input. A first NMOS transistor has the gate connected to the level shifting input and the source connected to ground. A first PMOS transistor has the gate connected to the level shifting output, the source connected to the high supply, and the drain connected to the first NMOS transistor drain. A second NMOS transistor has the gate connected to the inverted level shifting input, the source connected to ground, and the drain connected to the level shifting output. A second PMOS transistor has the gate connected to the first NMOS transistor drain, the source connected to the high supply, and the drain connected to the level shifting output. A third NMOS transistor has the gate connected to the first NMOS transistor drain, the source connected to the level shifting input, and the drain connected to the level shifting output. A fourth NMOS transistor has the gate connected to the second NMOS transistor drain, the source connected to the inverted level shifting input, and the drain connected to the first NMOS transistor drain.
Also in accordance with the objects of this invention, a new level shifting circuit, using dynamic voltage equalization, is described. An input swings between a low supply and ground. An output swings between a high supply and ground. An inverter has an input and an output. The input is connected to the input of the level shifting circuit, and the output forms an inverted level shifting input. A first NMOS transistor has the gate connected to the level shifting input and the source connected to ground. A first PMOS transistor has the gate connected to the level shifting output, the source connected to the high supply, and the drain connected to the first NMOS transistor drain. A second NMOS transistor has the gate connected to the inverted level shifting input, the source connected to ground, and the drain connected to the level shifting output. A second PMOS transistor has the gate connected to the first NMOS transistor drain, the source connected to the high supply, and the drain connected to the level shifting output. A transition pulse circuit has an output that is at ground during steady state and that pulses to the low supply for a short duration when the level shifting input changes state. A third NMOS transistor has the gate connected to the transition pulse circuit output, the source connected to the level shifting output, and the drain connected to the first NMOS transistor drain.